A semiconductor integrated circuit chip is typically fabricated with a back-end-of-line (BEOL) interconnect structure, which comprises multiple levels of metal lines and inter-level metal vias, to connect various integrated circuit components and devices that are fabricated as part of a front-end-of-line (FEOL) layer of the semiconductor integrated circuit chip. Current state of the art BEOL process technologies typically implement copper to form BEOL interconnects, as the use of copper material is known to significantly reduce resistance in the BEOL interconnect structure, resulting in improved conduction and higher performance. As copper interconnect structures are scaled down, however, there are significant increases in the resistivity and current density within the copper interconnect structures, which is undesirable. The increased current density in copper interconnect structures causes increased current-driven electromigration of copper atoms. In the context of copper interconnect structures, electromigration is the transport of the copper atoms caused by the gradual movement of ions in the copper material due to momentum transfer between conducting electrons and diffusing copper atoms. The electromigration of copper atoms can lead to various defects in copper interconnect structures such as voids and hillock defects.
The electrical conductivity and electromigration properties of a metallic interconnect depend, in part, on a grain microstructure of the metallic material which forms the metallic interconnect. For example, a polycrystalline microstructure is one which comprises many crystallites (or grains) of varying size and orientation, and with random texture and no grain direction. A polycrystalline microstructure tends to decrease the electrical conductivity of the metallic material, as well as increase electromigration within the metallic material due to the electron diffusion paths that exist along the various grain boundaries in the polycrystalline microstructure of the metallic material. In this regard, metallization layers are typically subjected to a thermal annealing process in which the metallic material is thermally annealed to promote recrystallization and grain growth of the microstructure of the metallic material, wherein the grain growth lowers energy by reducing grain boundary area, and the recrystallization lowers energy by eliminating mechanically strained grains. Since recrystallization and grain growth are both thermally activated processes involving atomic diffusion, it is desirable to anneal the metallic material at higher temperatures so as to reduce the anneal process time. However, it has been found that high temperature anneals can result in degraded interconnect reliability due to a phenomenon known as “stress voiding.”
In general, stress voiding occurs within a metallic interconnect as a result of thermal stress generation and relaxation during the thermal anneal process, which causes stress gradients within the metallic interconnect. In particular, during a thermal anneal process, significant compressive stress can be induced on metallic material within an etched opening in a dielectric layer due to coefficient of thermal expansion (CTE) mismatch between the CTE of the metallic material and the CTE of the surrounding dielectric material. When annealing a copper metallic interconnect at elevated temperatures, such as around 300 degrees C. and higher, an increasing compressive force is applied to the metallic material until a “stress relaxation point” is reached at a critical temperature, causing an increase in the atomic diffusion of the metallic material along the grain boundaries and towards a free surface of the metallic material to relieve the compressive stress. This atomic diffusion results in the formation of hillock defects on the free surface of the metallic material, as well as the formation of voids within lower regions of the metallic interconnect as the metallic interconnect is cooled. In this regard, the metallic interconnect is subjected to large tensile stresses as it cools to lower temperatures, resulting in the formation of stress voids within the metallic material at normal device operating temperatures. The formation of hillock defects and stress voids degrade the performance and reliability of metallic interconnect structures.